 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD78P324LP Datasheet(PDF) 37 Page - NEC |
|
|
|||||||||||||||||||||||||||||
UPD78P324LP Datasheet(HTML) 37 Page - NEC |
|
|
37 / 80 page  µPD78P324, 78P324(A) 37 (2) µPD78P324(A) Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Symbol Calculation formula MIN./MAX. Unit tSAST 0.5T–30 MIN. ns tHSTA 0.5T–30 MIN. ns tDAR T–40 MIN. ns tDAID (2.5+n) T–90 MAX. ns tDRID (1.5+n) T–75 MAX. ns tDSTR 0.5T–20 MIN. ns tDRA 0.5T–12 MIN. ns tWRL (1.5+n) T–40 MIN. ns tWSTH 0.5T–25 MIN. ns tDAW T–40 MIN. ns tDSTOD 0.5T+40 MAX. ns tDSTW 0.5T–20 MIN. ns tSODW 1.5T–40 MIN. ns tHWOD 0.5T–30 MIN. ns tDWST 0.5T–20 MIN. ns tWWL (1.5+n) T–40 MIN. ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
