LS7266R1 datasheet(6/14 Pages) LSI

6 / 14 page

7266R1-011498-6

Transient Characteristics. (TA = -25˚C to +80˚C, VDD = 4.5V to 5.5V)

Parameter

Symbol

Min. Value

Max.Value

Unit

Remarks

Read Cycle (See Fig. 1)

RD Pulse Width

tr1

CS Set-up Time

tr2

CS Hold Time

tr3

C/D Set-up Time

tr4

C/D Hold Time

tr5

X/Y Set-up Time

tr6

X/Y Hold Time

tr7

Data Bus Access Time

tr8

Access starts when both RD

and CS are low.

Data Bus Release Time

tr9

Release starts when either RD

or CS is terminated.

Back to Back Read delay

tr10

Write Cycle (See Fig. 2)

WR Pulse Width

tW1

CS Set-up Time

tW2

CS Hold Time

tW3

C/D Set-up Time

tW4

C/D Hold Time

tW5

X/Y Set-up Time

tW6

X/Y Hold Time

tW7

Data Bus Set-up Time

tW8

Data Bus Hold Time

tW9

Back to Back Write Delay

tW10

Quadrature Mode (See Fig. 3-5)

FCK High Pulse Width

FCK Low Pulse Width

FCK Frequency

fFCK

MHz

Mod-n Filter Clock(FCKn)Period

t3 = (n+1) (t1+t2), where

n = PSC = 0 to FFH

FCKn frequency

fFCKn

MHz

Quadrature Separation

≥ 2t3

Quadrature Clock Pulse Width

115

≥ 4t3

Quadrature Clock frequency

fQA, fQB

4.3

MHz

fQA = fQB = 1/8t3

Quadrature Clock to Count Delay

tQ1

5t3

6t3

X1/X2/X4 Count Clock Pulse Width tQ2

tQ2 = t3

Index Input Pulse Width

tidx

≥ 3t3

Index Skew from A

tAi

≤ t3

Carry/Borrow/Compare Output Width

tQ3

tQ3 = t3

Non-Quadrature Mode (See Fig. 6-7)

Clock A - High Pulse Width

Clock A - Low Pulse Width

Direction Input B Set-up Time

t8S

Direction Input B Hold Time

t8H

Gate Input (ABG) Set-up Time

tGS

Gate Input (ABG) Hold Time

tGH

Clock Frequency (non-Mod-N)

MHz

fA = (1/ (t6 + t7) )

Clock Frequency (Mod-N)

fAN

MHz

Clock to Carry or Borrow Out Delay

Carry or Borrow Out Pulse Width

t10

t10 = t7

Load CNTR, Reset CNTR and

Load OL Pulse Width

t11

Clock to Compare Out Delay

t12

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