LT3753_15 datasheet(21/36 Pages) LINER

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LT3753

3753f

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applicaTions inForMaTion

As shown in Figure 12, the maximum steady-state value

for VCCL may occur at minimum or maximum input volt-

age. Hence VCCLshouldbecalculatedatbothinputvoltage

levels and the largest of the two calculations used. M1

drain should be rated for a voltage greater than the above

steady-state VDS calculation due to tolerances in duty

cycle, load transients, voltage ripple on CCL and leakage

inductance spikes. CCL should be rated higher due to the

effect of voltage coefficient on capacitance value. A typical

choice for CCL is a good quality X7R capacitor. M2 should

have a VDS rating greater than VCCL since the bottom plate

of CCL is –VCCL during M1 on and M2 off. For high input

voltage applications, the limited VDS rating of available

P-channel MOSFETs might require changing from a LO

side to HI side active clamp topology.

Forthelosideactiveclamptopologyinsteadystate,during

M1 on time, magnetizing current (IMAG) increases from a

negative value to a positive value (Figure 11). When M1

turnsoff,magnetizingcurrentchargesSWPuntilitreaches

VCCL plus the voltage drop of the M2 body diode. At this

Figure 12. LO Side VCCL vs Duty Cycle

(Normalized to 50% Duty Cycle)

Figure 11. Active Clamp Reset: Magnetizing

Current and M1 Drain Voltage

20µs/DIV

IMAG

1A/DIV

SWP

50V/DIV

3753 F11

DUTY CYCLE (%)

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

3753 F12

LO SIDE ACTIVE CLAMP TOPOLOGY

Figure 13. HI Side VCCL vs Duty Cycle

(Normalized to 50% Duty Cycle)

Figure 14. HI Side Active Clamp Topology (Using LT3752-1)

DUTY CYCLE (%)

1.5

3753 F13

1.0

0.5

2.0

2.5

1.3

0.8

1.8

2.3

HI SIDE ACTIVE CLAMP TOPOLOGY

CCL

LLEAK

SWP

LMAG

FSW

CSW

• •

–VIN

OUT

VIN

–VIN

VOUT

–VOUT

AOUT

LT3752-1

LTXXXX

3753 F14

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