CMLDM8002A

CMLDM8002AG*

CMLDM8002AJ

SURFACE MOUNT SILICON

DUAL P-CHANNEL

ENHANCEMENT-MODE

MOSFETS

SOT-563 CASE - MECHANICAL OUTLINE

LEAD CODE:

1) Gate Q1

2) Source Q1

3) Drain Q2

4) Gate Q2

5) Source Q2

6) Drain Q1

MARKING CODES:

CMLDM8002A: C08

CMLDM8002AG*: CG8

LEAD CODE:

1) Source Q1

2) Gate Q1

3) Drain Q2

4) Source Q2

5) Gate Q2

6) Drain Q1

MARKING CODE: CJ8

CMLDM8002A (USA Pinout)

CMLDM8002AG*

CMLDM8002AJ (Japanese Pinout)

ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted)

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

rDS(ON)

VGS=10V, ID=500mA

2.5

Ω

rDS(ON)

VGS=10V, ID=500mA, TJ=125°C

4.0

Ω

rDS(ON)

VGS=5.0V, ID=50mA

3.0

Ω

rDS(ON)

VGS=5.0V, ID=50mA, TJ=125°C

5.0

Ω

gFS

VDS =10V, ID=200mA

200

mS

Crss

VDS=25V, VGS=0, f=1.0MHz

7.0

pF

Ciss

VDS=25V, VGS=0, f=1.0MHz

70

pF

Coss

VDS=25V, VGS=0, f=1.0MHz

15

pF

Qg(tot)

VDS=25V, VGS=4.5V, ID=100mA

0.72

nC

Qgs

VDS=25V, VGS=4.5V, ID=100mA

0.25

nC

Qgd

VDS=25V, VGS=4.5V, ID=100mA

0.16

nC

ton, toff

VDD=30V, VGS=10V, ID=200mA

RG=25Ω, RL=150Ω

20

ns

* Device is Halogen Free by design

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R7 (8-June 2015)