RT8487 datasheet(11/13 Pages) RICHTEK

11 / 13 page

RT8487

is a registered trademark of Richtek Technology Corporation.

DS8487-00

March

2015

www.richtek.com

OCP threshold which is about seven times of the sense

voltage threshold.

Thermal Protection (OTP)

A thermal protection feature is included to protect the

RT8487 from excessive heat damage. When the

junction

temperature exceeds a threshold of 150

C, the thermal

protection OTP will be triggered and the GATE will be

turned off.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature.

The maximum power dissipation can be calculated by

the following formula :

PD(MAX) = (TJ(MAX)  TA) / JA

where TJ(MAX) is the maximum junction temperature,

TA is the ambient temperature, and JA is the junction to

ambient thermal resistance.

For recommended operating condition specifications,

the maximum junction temperature is 125

C. The

junction to ambient thermal resistance,

JA, is layout

dependent. For TSOT-23-6 package, the thermal

resistance,

JA, is 197.4C/W on a standard JEDEC

51-7 four-layer thermal test board. The maximum

power dissipation at TA = 25C can be calculated by

the following formula :

PD(MAX) = (125C  25C) / (197.4C/W) = 0.5W for

TSOT-23-6 package

The maximum power dissipation depends on the

operating ambient temperature for fixed TJ(MAX) and

thermal resistance,

JA. The derating curve in Figure 1

allows the designer to see the effect of rising ambient

temperature on the maximum power dissipation.

Figure 1. Derating Curve of Maximum Power

Dissipation

Layout Considerations

For best performance of the RT8487, the following

layout guidelines should be strictly followed.



The hold up capacitor, C1, must be placed as close

as possible to the VCC pin.



The compensation capacitor, C2, and delay resistor,

R3B, must be placed as close as possible to the VC

and the AND pin.



The IC GATE and GND pin are high frequency

switching nodes.

Both traces must be as wide and

short as possible.



Keep the main traces with switching current as short

and wide as possible.



Place CIN, L1, Q1, RS, COUT, and D1 as close to

each other as possible.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

100

125

Ambient Temperature (°C)

Four-Layer PCB

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