+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

12

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Internal Clock

In internal clock mode, the MAX1245 generates its own

conversion clock internally. This frees the µP from the

burden of running the SAR conversion clock and allows

the conversion results to be read back at the proces-

sor’s convenience, at any clock rate from zero to

1.5MHz. SSTRB goes low at the start of the conversion

and then goes high when the conversion is complete.

SSTRB will be low for a maximum of 7.5µs (

SHDN =

FLOAT), during which time SCLK should remain low for

best noise performance.

An internal register stores data when the conversion is

in progress. SCLK clocks the data out of this register at

any time after the conversion is complete. After SSTRB

goes high, the next falling clock edge produces the

MSB of the conversion at DOUT, followed by the

remaining bits in MSB-first format (Figure 9).

CS does

not need to be held low once a conversion is started.

Pulling

CS high prevents data from being clocked into

the MAX1245 and three-states DOUT, but it does not

adversely affect an internal clock-mode conversion

already in progress. When internal clock mode is

• • •

• • •

• • •

• • •

PD0 CLOCKED IN

SSTRB

SCLK

CS

• • •

• • • •

•

Figure 8. External-Clock-Mode SSTRB Detailed Timing

• • •

• • •

• • •

• • •

CS

SCLK

DIN

DOUT

Figure 7. Detailed Serial-Interface Timing