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74LV4053 Datasheet(PDF) 14 Page - NXP Semiconductors |
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74LV4053 Datasheet(HTML) 14 Page - NXP Semiconductors |
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14 / 27 page ![]() 74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 18 September 2014 14 of 27 NXP Semiconductors 74LV4053 Triple single-pole double-throw analog switch Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 15. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aak353 VEXT VCC VEE VI VO DUT CL RT RL RL G Table 10. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ < 2.7 V VCC 6 ns 50 pF 1 k open VEE 2VCC 2.7 V to 3.6 V 2.7 V 6 ns 15 pF, 50 pF 1 k open VEE 2VCC > 3.6 V VCC 6 ns 50 pF 1 k open VEE 2VCC |
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