MAX5202ACUB datasheet(4/13 Pages) MAXIM

4 / 13 page

Low-Cost, Voltage-Output, 16-Bit DACs with

Internal Reference in µMAX

_______________________________________________________________________________________

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE (Note 1)

Resolution

Bits

MAX520_AEUB

±10

±20

MAX520_ACUB

±10

±20

Integral Nonlinearity (Note 2)

INL

MAX520_BEUB

±20

±40

LSB

MAX520_A_UB (Note 3)

±1

MAX520_BEUB (0°C to +105°C) (Note 3)

±1

Differential Nonlinearity

(Note 2)

DNL

MAX520_BEUB (-40°C to 0°C)

±2

LSB

Offset Error

Inferred from measurement at 3800 hex and

FFFF hex

±3

±25

Gain Error

Within DAC output range (Note 4)

±0.01

±1.0

%FSR

Power-Supply Rejection

PSR

VDD = 3V ±10%, midscale input

±0.06

±0.5

mV/V

DYNAMIC PERFORMANCE

DAC Output Range

(Note 2)

0 to

VDD

Voltage-Output Slew Rate

0.6

V/µs

Output Settling Time

To ±1 LSB of FS,

VSTEP = 0.25 ✕ VREF to 0.75 ✕ VREF

µs

Output Noise

Code = 8400 hex, 10kHz

175

nV/

√Hz

Reference Feedthrough

Code = 0000 hex at 100kHz, VREF = 1VP-P

mVP-P

DAC Glitch Impulse

Major carry transition (code 7FFF hex to

code 8000 hex)

⋅s

Digital Feedthrough

Code = 0000 hex; CS = VDD;

LDAC = 0; SCLK, DIN = 0 or VDD levels

⋅s

Wake-Up Time

From software shutdown to 90% of output

code = FFFF hex

µs

Power-Up Time

From power applied to 90% of output

code = FFFF hex

ELECTRICAL CHARACTERISTICS—MAX5202/MAX5203

(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10k

Ω in parallel with 250pF, TA = TMIN to TMAX, unless otherwise

noted. Typical values are at TA = +25°C.)

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