TSI721 datasheet(21/68 Pages) IDT

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2. Signals > Pinlist

Tsi721 Datasheet

May 5, 2014

Formal Status

This document is confidential and is subject to an NDA.

Integrated Device Technology

2.3

Pinlist

For a list-based version of Tsi721’s pin to signal mapping, see the Tsi721 Ballmap and Pinlist.

2.4

PCIe Signals

Table 2: PCIe Signals

Name

Pin Type

Description

PCTP[3:0]

PCTN[3:0]

PCIE_O

Differential transmit data for the PCIe port.

PCRP[3:0]

PCRN[3:0]

PCIE_I

Differential receive data for the PCIe port.

PCCLKP

PCCLKN

DIFF_I

PCIe reference clock input.

When in PCIe common clock mode (CLKMOD pin is high, see the “Clocking”

chapter in the Tsi721 User Manual), PCCLKP/N requires a clock frequency of

100 MHz.

When in PCIe non-common clock mode (CLKMOD pin is low), PCCLKP/N

requires a clock frequency as selected by CLKSEL[1:0], and must have the

same clock frequency as REFCLKP/N.

PCRSTOn

It is an output for normal operation and an input during scan test mode.

As an asynchronous active-low reset output, this pin is low when the following

occurs:

• The PCIe port detects hot reset

• The PCIe port is DL_DOWN

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