IRS2453D datasheet(13/18 Pages) IRF

13 / 18 page

IRS2453(1)D(S)

www.irf.com

November 28, 2012

Functional Description

Under-Voltage Lock-Out Mode (UVLO)

The under-voltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on

threshold of the IC. The IRS2453(1)D under-voltage lock-out is designed to maintain an ultra low supply current of

e the high and low side output drivers are

activated. During under-voltage lock-out mode, the high and low side driver outputs LO1, LO2, HO1, HO2 are all

low. With VCC above the VCCUV+ threshold, the IC turns on and the output begin to oscillate.

Normal Operating Mode

Once VCC reaches the start-up threshold VCCUV+, the MOSFET M1 opens, RT increases to approximately VCC

(VCC-VRT+) and the external CT capacitor starts charging. Once the CT voltage reaches VCT- (about 1/3 of VCC),

established by an internal resistor ladder, LO1 and HO2 turn on with a delay equivalent to the dead time (td).

Once the CT voltage reaches VCT+ (approximately 2/3 of VCC), LO1 and HO2 go low, RT goes down to

approximately ground (VRT-), the CT capacitor starts discharging and the dead time circuit is activated. At the end

of the dead time, LO2 and HO1 go high. Once the CT voltage reaches VCT-, LO2 and HO1 go low, RT goes to

high again, the dead time is activated. At the end of the dead time, LO1 and HO2 go high and the cycle starts

over again.

The frequency is best determined by the graph, Frequency vs. RT, page 3, for different values of CT. A first order

approximate of the oscillator frequency can also be calculated by the following formula:





453

This equation can vary slightly from actual measurements due to internal comparator over- and under-shoot

delays.

Bootstrap MOSFET

The internal bootstrap FET and supply capacitor (CBOOT) comprise the supply voltage for the high side driver

circuitry. The internal bootstrap FET only turns on when the corresponding LO is high. To guarantee that the high-

side supply is charged up before the first pulse on HO1 and HO2, LO1 and LO2 outputs are both high when CT

ramps between zero and 1/3*VCC. LO1 and LO2 are also high when CT is grounded below 1/6*VCC to ensure that

the bootstrap capacitor is charged when CT is brought back over 1/3*VCC.

Non-Latched Shutdown

If CT is pulled down below VCTSD (approximately 1/6 of VCC) by an external circuit, CT is not able to charge up

and oscillation stops. HO1 and HO2 outputs are held low. LO1 and LO2 outputs remain high while VCT remains

below VCT- enabling the bootstrap capacitors to charge. This state remains until the CT input is released and

oscillation can resume.

Latched Shutdown

When the SD pin is brought above 2 V, the IC goes into fault mode and all outputs are low. VCC has to be recycled

below VCCUV- to restart. The SD pin can be used for over-current or over-voltage protection using appropriate

external circuitry.

IRS2453D Datasheet(PDF) 13 Page - International Rectifier