_______________Definitions of Terms

Period: The time elapsed between the first pulse’s

leading edge and the following pulse’s leading edge.

between the 1.5V level on the leading edge and the

1.5V level on the trailing edge, or vice-versa.

the 20% and 80% points on the input pulse’s leading

edge.

the 80% and 20% points on the input pulse’s trailing

edge.

the 1.5V level on the input pulse’s leading edge and the

corresponding output pulse’s leading edge.

the 1.5V level on the input pulse’s trailing edge and the

corresponding output pulse’s trailing edge.

____________________Test Conditions

Ambient Temperature:

+25°C ±3°C

+5V ±0.01V

Input Pulse:

High = 3.0V ±0.1V

Low = 0.0V ±0.1V

Source Impedance:

50

Ω max

Rise and Fall Times:

3.0ns max

Pulse Width:

500ns max

Period:

1µs

Each output is loaded with a 74F04 input gate. Delay is

measured at the 1.5V level on the rising and falling

edges. The time delay due to the 74F04 is subtracted

from the measured delay.

5-Tap Silicon Delay Line

4

_______________________________________________________________________________________

______________________________________________________________Pin Description

1

1

Signal Input

14-PIN DIP

FUNCTION

8-PIN

DIP/SO/µMAX

NAME

16-PIN SO

2

4

40% of specified maximum delay

4

1

IN

TAP2

3

PIN

6

80% of specified maximum delay

4

7

Device Ground

8

6

TAP4

GND

5

8

100% of maximum specified delay

6

10

60% of specified maximum delay

11

9

TAP5

TAP3

7

12

20% of specified maximum delay

8

14

Power-Supply Input

16

13

TAP1

—

2, 3, 5, 9, 11,

13

No Connection. Not internally connected.

2, 3, 5, 7, 10,

12, 14, 15

N.C.

Note: Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.