ULA1145

Preliminary

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

8 of 10

www.unisonic.com.tw

QW-R106-006.a



SD OUTPUT CIRCUIT(Cont.)

(1) Current path during detuning

C

12

9

12

9

C

(2) Current return path from detuning

9

C

12

I=0

As can be seen from the above circuit diagrams, the time constant during detuning is determined by the internal

PNP resistance, the NPN collector resistance and the capacitance of the externally-mounted capacitor. This time

constant is determined by the external resistance RAFC and capacitor

C. This time constant, τ = RAFC×C, must be set depending on the required search time.

3. Narrow-band SD output circuit

An IF count circuit is provided for equipment compatibility for the European marketplace. However, if the band is

made narrow using only the SD circuit, there is a tendency for the number of erroneous stops caused by an

undesired signal to increase. To prevent this, two threshold voltages should be used to control the SD circuit.