AM1806 datasheet(98/245 Pages) TI

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AM1806

SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014

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Table 6-21. Timing Requirements for EMIFA Asynchronous Memory Interface (1)

1.2V

1.1V

1.0V

NO.

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

READS and WRITES

tc(CLK)

Cycle time, EMIFA module clock

6.75

13.33

tw(EM_WAIT)

Pulse duration, EM_WAIT assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EM_D[15:0] valid before EM_OE high

th(EMOEH-EMDIV)

Hold time, EM_D[15:0] valid after EM_OE high

tsu (EMOEL-

Setup Time, EM_WAIT asserted before end of Strobe

4E+3

EMWAIT)

Phase

WRITES

tsu (EMWEL-

Setup Time, EM_WAIT asserted before end of Strobe

4E+3

EMWAIT)

Phase

(1)

E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when

SYSCLK3 is selected and set to 100MHz, E=10ns

Peripheral Information and Electrical Specifications

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