ZL2102ALAFTK datasheet(13/58 Pages) INTERSIL

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ZL2102

FN8440.2

November 20, 2014

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as an input, an output, or auto-detect mode. The ZL2102

incorporates an internal phase-locked loop (PLL) to clock the

internal circuitry. The PLL can be driven by an external clock

source connected to the SYNC pin, or it can be configured to drive

the internal clock out of the SYNC pin to other devices.

SYNC OUTPUT: When the SYNC pin is configured as an output, the

device will run from its internal oscillator and will drive the

selected switching frequency onto the SYNC pin so that other

devices can be synchronized to it.

SYNC INPUT: When the SYNC pin is configured as an input, the

device will check for an external clock signal on the SYNC pin

each time the output is enabled. The internal oscillator will then

synchronize with the rising edge of the external clock. The

incoming clock signal must be in the range of 200kHz to 1MHz

and must be stable when the enable pin is asserted. The clock

signal must have a minimum width of 150ns, and it must stay

within 10% of its initial value. In the event of a loss of the

external clock signal, will automatically switch to its internal

oscillator and switch at a frequency close to the previous

incoming frequency. The output voltage may show a transient

overshoot/undershoot if this occurs.

SYNC AUTO DETECT: When the SYNC pin is configured in

auto-detect mode, the device will check for a clock signal on the

SYNC pin each time EN is asserted. If there is a valid clock, the

pin will run as a sync input.

If no incoming clock signal is present, the device will switch at

the selected internal clock rate.

Soft-Start and UVLO Settings (SS)

The ZL2102 supports variable turn-on/off delay times,

turn-on/off ramp rates, and input undervoltage lockout (UVLO)

functions. These features may be used as part of an overall

in-rush current management strategy or to precisely control how

fast a load is turned on. The ZL2102 provides several options for

precisely and independently controlling both the delay and ramp

time periods.

The soft-start delay period begins when the EN pin is asserted

and ends when the delay time expires. The soft-start ramp timer

enables a precisely controlled monotonic ramp to the nominal

VOUT value that begins once the delay period has expired. This

process is also followed for ramp down after the EN pin has been

deasserted.

The input undervoltage lockout (UVLO) prevents the ZL2102 from

operating when the input falls below a preset threshold,

indicating the input supply is out of its specified range.

The ZL2102's TON/TOFF delay time, TON/TOFF ramp time, and

UVLO functions can be configured using the SS pin strap options

shown in Table 7.

These functions can also be set independently using TON_DELAY,

TON_RISE, TOFF_DELAY, and TOFF_FALL PMBus commands. The

UVLO threshold can be adjusted using the VIN_UV_FAULT_LIMIT

PMBus command. The ramp down function is disabled by

default, but it can be enabled using the ON_OFF_CONFIG or

OPERATION PMBus commands depending on the desired device

enable method.

Start-up Procedure

The ZL2102 follows a specific internal start-up procedure after

power is applied. Figure 12 describes the start-up sequence.

TABLE 7.

RSS

(kΩ)

TON/TOFF DELAY

TIME

(ms)

TON/TOFF

RAMP TIME

(ms)

UVLO

(V)

4.5

12.1

LOW or 13.3

14.7

16.2

17.8

19.6

21.5

23.7

5.5

26.1

HIGH or 28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

7.5

OPEN or 61.9

68.1

82.5

100

110

121

ZL2102ALAFTK Datasheet(PDF) 13 Page - Intersil Corporation

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