BLOCK DIAGRAM

C

SY100S360

DUAL PARITY

CHECKER/

GENERATOR

s Max. propagation delay of 2200ps

s Industry standard 100K ECL levels

s Extended supply voltage option:

s Voltage and temperature compensation for improved

noise immunity

s Internal 75K

s 15% faster than Fairchild 300K

s Approximately 30% lower power than Fairchild 300K

s Function and pinout compatible with Fairchild F100K

s Available in 24-pin CERPACK and 28-pin PLCC

packages

FEATURES

DESCRIPTION

The SY100S360 is a dual parity checker/generator and

is designed for use in high-performance ECL systems. The

inputs are segmented into two groups of nine inputs each

and the parity output is at a logic LOW when an even

number of inputs are at a logic HIGH. In each group, one of

the nine inputs (Ia, Ib) has a shorter propagation delay and,

therefore, is ideal as the expansion input for parity

generation of wider data.

A Compare output (C) is also provided which allows

comparison of two 8-bit words. A logic LOW on the C output

indicates a match. The inputs on this device have 75K

Ω

pull-down resistors.

Rev.: G

Amendment: /0

Issue Date:

July, 1999

C

4

3

2

1

28

27

12

13

14

15

16

17

19

11

20

10

21

9

22

8

23

7

24

6

Top View

PLCC

J28-1

26

18

25

5

18

17

16

15

14

13

1

2

3

4

5

6

7

24

8

23

9

22

10

21

11

20

12

19

Top View

Flatpack

F24-1

PIN CONFIGURATIONS

1