PIC16CE623 datasheet(59/108 Pages) MICROCHIP

59 / 108 page

Preliminary

DS40182A-page 59

PIC16CE62X

10.5

Interrupts

The PIC16CE62X has 4 sources of interrupt:

• External interrupt RB0/INT

• TMR0 overﬂow interrupt

• PortB change interrupts (pins RB7:RB4)

• Comparator interrupt

The interrupt control register (INTCON) records

individual interrupt requests in ﬂag bits. It also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which

re-enable RB0/INT interrupts.

The INT pin interrupt, the RB port change interrupt and

the TMR0 overﬂow interrupt ﬂags are contained in the

INTCON register.

The peripheral interrupt ﬂag is contained in the special

contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt

ﬂag bits. The interrupt ﬂag bit(s) must be cleared in soft-

ware before re-enabling interrupts to avoid RB0/INT

recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends

when

the

interrupt

event

occurs

(Figure 10-16). The latency is the same for one or two

cycle instructions. Once in the interrupt service routine

the source(s) of the interrupt can be determined by

polling the interrupt ﬂag bits. The interrupt ﬂag bit(s)

must be cleared in software before re-enabling inter-

rupts to avoid multiple interrupt requests. Individual

interrupt ﬂag bits are set regardless of the status of

their corresponding mask bit or the GIE bit.

Note 1:

Individual interrupt ﬂag bits are set

regardless

the

status

their

corresponding mask bit or the GIE bit.

When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a

NOP in the cycle immediately following

the instruction which clears the GIE bit.

The interrupts which were ignored are

still pending to be serviced when the GIE

bit is set again.

FIGURE 10-15: INTERRUPT LOGIC

RBIF

RBIE

T0IF

T0IE

INTF

INTE

GIE

PEIE

Wake-up

(If in SLEEP mode)

Interrupt

to CPU

CMIE

CMIF

62X.bk Page 59 Tuesday, March 10, 1998 3:40 PM

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