PIC18C601ESLASHPT datasheet(64/320 Pages) MICROCHIP

64 / 320 page

PIC18C601/801

DS39541A-page 64

Advance Information

 2001 Microchip Technology Inc.

5.2

8-bit Mode

The External Memory Interface can operate in 8-bit

mode. The mode selection is not software configurable,

but is programmable via the configuration bits.

There are two types of connections in 8-bit mode. They

are referred to as:

• 8-bit Multiplexed

• 8-bit De-Multiplexed

5.2.1

8-BIT MULTIPLEXED MODE

The 8-bit Multiplexed mode applies only to the

PIC18C601. Data and address lines are multiplexed on

port pins and must be decoded with glue logic.

For 8-bit Multiplexed mode on the PIC18C601, the

instructions will be fetched as two 8-bit bytes on a

shared data/address bus (PORTD). The two bytes are

sequentially fetched within one instruction cycle (TCY).

Therefore, the designer must choose external memory

devices according to timing calculations based on 1/2

Tcy (2 times instruction rate). For proper memory

speed selection, glue logic propagation delay times

must be considered along with setup and hold times.

The Address Latch Enable (ALE) pin indicates that the

address bits A<7:0> are available on the External

Memory Interface bus. The OE output enable signal will

enable one byte of program memory for a portion of the

instruction cycle, then BA0 will change and the second

byte will be enabled to form the 16-bit instruction word.

The least significant bit of the address, BA0, must be

connected to the memory devices in this mode.

Figure 5-1 shows an example of 8-bit Multiplexed

mode on the PIC18C601. The control signals used in

8-bit Multiplexed mode are outlined in Table 5-1.

FIGURE 5-1:

8-BIT MULTIPLEXED MODE EXAMPLE

TABLE 5-1:

8-BIT MULTIPLEXED MODE CONTROL SIGNALS

AD<7:0>

PIC18C601

BA0

WRL

373

A<x:1>

D<7:0>

OE WR(2)

ALE

D<7:0>

A<17:0>

Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.

A16, AD<15:8>

CS1

Name

8-bit Mux

Mode

Function

RG0/ALE

ALE

Address Latch Enable (ALE) control pin

RG1/OE

Output Enable (OE) control pin

RG2/WRL

WRL

Write Low (WRL) control pin

RG4/BA0

BA0

Byte address bit 0

RF3/CSIO

CSIO

Chip Select I/O (See Section 5.4)

RF5/CS1

CS1

Chip Select 1 (See Section 5.4)

PIC18C601E/PT Datasheet(PDF) 64 Page - Microchip Technology

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