PIC18F010T-ISLASHP datasheet(69/176 Pages) MICROCHIP

69 / 176 page

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 67

PIC18F010/020

9.0

I/O PORT

Depending on the device options enabled, there are as

many as six general purpose I/O pins available. Some of

the pins are multiplexed with alternative functions from

the peripheral features on the device. Thus, when a

peripheral is enabled, the associated pin may not be

used as a general purpose I/O pin. On a Power-on Reset,

all pins configured as general I/O are set as inputs.

9.1

PORTB, TRISB, and LATB Registers

PORTB is a 6-bit wide, bi-directional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB pin

an input (i.e., put the corresponding output driver in a Hi-

Impedance mode). Clearing a TRISB bit (= 0) will make

the corresponding PORTB pin an output (i.e., put the

contents of the output latch on the selected pin). On a

Power-on Reset, these pins are configured as inputs.

Example 9-1 demonstrates PORTB configuration.

EXAMPLE 9-1:

INITIALIZING PORTB

Read-modify-write operations on the LATB register,

read and write the latched output value for PORTB.

Figure 9-1 shows a simplified block diagram of the

PORTB/LATB/TRISB operation.

FIGURE 9-1:

SIMPLIFIED BLOCK

DIAGRAM OF PORT/LAT/

TRIS OPERATION

9.2

Additional Functions

Each pin is multiplexed with other functions. Refer to

Table 9-1 for information about individual pin functions.

9.2.1

WEAK PULL-UP

Each of the PORTB pins has an individually config-

urable weak internal pull-up. Control bits WPUBx

enable or disable each pull-up (see Register 9-1). Each

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are dis-

abled on a Power-on Reset.

9.2.2

INTERRUPT-ON-CHANGE

Each of the PORTB pins is individually configurable as

an interrupt-on-change pin. Control bits IOCBx enable

or disable the interrupt function for each pin (see

Power-on Reset.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTB. The "mismatch" outputs of the last read are

OR’d together to set, or clear the RB Port Change Inter-

rupt flag bit RBIF, in the INTCON register.

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of PORTB (except with MOVFF

instruction). This will end the mismatch condition.

Clear the flag bit RBIF.

9.2.3

RB2/T0CLK/INT0

The RB2 pin is configurable to function as a general

I/O, the clock input for TIMER0, or as an external edge

triggered interrupt. Figure 9-2 shows the block diagram

of this I/O pin. Refer to Section 8.0 for details about

interrupts and Section 10.0 for details about TIMER0.

9.2.4

RB3/MCLR/VPP

The RB3 pin is configurable to function as general I/O

or as the RESET pin, MCLR. This pin is open drain

when configured as an output. Refer to Figure 9-3 for a

block diagram of the I/O pin.

9.2.5

RB4/OSC2/CLKOUT

The RB4 pin is configurable to function as a general

I/O pin, oscillator connection, or as a clock output.

Figure 9-4 shows the block diagram of this I/O pin.

Refer to Section 2.0 for clock/oscillator information.

9.2.6

RB5/OSC1/CLKIN

The RB5 pin is configurable to function as a general

I/O pin, oscillator connection, or a clock input pin.

Figure 9-5 shows a block diagram of this I/O pin. Refer

to Section 2.0 for clock /oscillator information.

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

CLRF

LATB

; Alternate method

; to clear output

; data latches

MOVLW

0x03

; Value used to

; initialize data

; direction

MOVWF

TRISB

; Set RB1:RB0 as inputs

; RB5:RB2 as outputs

WR LAT +

Data Latch

I/O pin

RD Port

WR Port

TRIS

RD LAT

Data Bus

Note:

The voltage on RB3 open drain output

must not exceed VDD.

PIC18F010T-I/P Datasheet(PDF) 69 Page - Microchip Technology

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