PIC16F628-04SLASHSS datasheet(92/160 Pages) MICROCHIP

92 / 160 page

PIC16F62X

DS40300B-page 92

Preliminary

13.2

EECON1 AND EECON2 REGISTERS

EECON1 is the control register with five low order bits

physically implemented. The upper-three bits are non-

existent and read as ’0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit

is set when a write operation is interrupted by a MCLR

reset or a WDT time-out reset during normal opera-

tion. In these situations, following reset, the user can

check the WRERR bit and rewrite the location. The

data and address will be unchanged in the EEDATA

and EEADR registers.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ’0’s. The EECON2 register is used

exclusively in the Data EEPROM write sequence.

UUUU

R/W-x

R/W-0

R/S-0

R/S-x

—

WRERR

WREN

R = Readable bit

W = Writable bit

S = Settable bit

U = Unimplemented bit,

read as ‘0’

-n = Value at POR reset

bit7

bit0

bit 7:4

Unimplemented: Read as '0'

bit 3

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated

(any MCLR reset, any WDT reset during normal operation or BOD detect)

= The write operation completed

bit 2

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the data EEPROM

bit 1

WR: Write Control bit

= initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only

be set (not cleared) in software.

= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be

set (not cleared) in software).

= Does not initiate an EEPROM read

PIC16F628-04/SS Datasheet(PDF) 92 Page - Microchip Technology

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