1.45 x 10

-7

- 1.4

1.45 x 10

-7

-

-7

1.45 x 10

-7

+ 50 ns

LM5085, LM5085-Q1

www.ti.com

SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015

7.3 Feature Description

7.3.1 Regulation Control Circuit

The LM5085 buck DC-DC controller employs a control scheme based on a comparator and a one-shot on-timer,

with the output voltage feedback compared to an internal reference voltage (1.25V). When the FB pin voltage

falls below the feedback reference, Q1 is switched on for a time period determined by the input voltage and a

in the Block Diagram). The regulated output voltage is calculated as follows:

(2)

The feedback voltage supplied to the FB pin is applied to a comparator rather than a linear amplifier. For proper

operation sufficient ripple amplitude is necessary at the FB pin to switch the comparator at regular intervals with

minimum delay and noise susceptibility. This ripple is normally obtained from the output voltage ripple attenuated

through the feedback resistors. The output voltage ripple is a result of the inductor’s ripple current passing

through the output capacitor’s ESR, or through a resistor in series with the output capacitor. Multiple methods are

available to ensure sufficient ripple is supplied to the FB pin, and three different configurations are discussed in

the Typical Application section.

When in regulation, the LM5085 operates in continuous conduction mode at medium to heavy load currents and

discontinuous conduction mode at light load currents. In continuous conduction mode the inductor’s current is

always greater than zero, and the operating frequency remains relatively constant with load and line variations.

The minimum load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. In

discontinuous conduction mode, where the inductor’s current reaches zero during the off-time, the operating

frequency is lower than in continuous conduction mode and varies with load current. Conversion efficiency is

maintained at light loads since the switching losses are reduced with the reduction in load and frequency.

over-voltage comparator immediately switches off Q1. The next on-time period starts when the voltage at FB falls

below the feedback reference voltage.

7.3.2 On-Time Timer

(3)

section). The buck regulator effective on-time, measured at the SW node (junction of Q1, L1, and D1) is typically

longer than that calculated in Equation 3 due to the asymmetric delay of the PFET. The on-time difference

caused by the PFET switching delay can be estimated as the difference of the turn-off and turn-on delays listed

in the PFET data sheet. Measuring the difference between the on-time at the PGATE pin versus the SW node in

the actual application circuit is also recommended.

(4)

(5)

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