SW

L

LM2696

GND

FB

CBOOT

SS

RON

SD

PGOOD

LM2696

www.ti.com

SNVS375B – OCTOBER 2005 – REVISED APRIL 2013

PRE-BIAS LOAD STARTUP

Should the LM2696 start into a pre-biased load the output will not be pulled low. This is because the part is

asynchronous and cannot sink current. The part will respond to a pre-biased load by simply enabling PWM high

or extending the off-time until regulation is achieved. This is to say that if the output voltage is greater than the

regulation voltage the off-time will extend until the voltage discharges through the feedback resistors. If the load

voltage is greater than the regulation voltage, a series of pulses will charge the output capacitor to its regulation

voltage.

THERMAL CONSIDERATIONS

The thermal characteristics of the LM2696 are specified using the parameter

temperature to the ambient temperature. While the value of

(including board thickness, number of layers, orientation, etc), it provides the user with a common point of

reference.

To obtain an estimate of a devices junction temperature, one may use the following relationship:

Where

•

•

•

•

(32)

LAYOUT CONSIDERATIONS

The LM2696 regulation and under-voltage comparators are very fast and will respond to short duration noise

pulses. Layout considerations are therefore critical for optimum performance. The components at pins 5, 6, 7, 12

and 13 should be as physically close as possible to the IC, thereby minimizing noise pickup in the PC traces. If

the internal dissipation of the LM2696 produces excessive junction temperatures during normal operation, good

use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad on the bottom of

the HTSSOP-16 package can be soldered to a ground plane on the PC board, and that plane should extend out

from beneath the IC to help dissipate the heat. Use of several vias beneath the part is also an effective method

of conducting heat. Additionally, the use of wide PC board traces, where possible, can also help conduct heat

away from the IC. Judicious positioning of the PC board within the end product, along with use of any available

air flow (forced or natural convection) can help reduce the junction temperatures. Traces in the power plane

(Figure 26) should be short and wide to minimize the trace impedance; they should also occupy the smallest

area that is reasonable to minimize EMI. Sizing the power plane traces is a tradeoff between current capacity,

inductance, and thermal dissipation. For more information on layout considerations, please refer to TI Application

Note AN-1229.

Figure 26. Bold Traces Are In The Power Plane

Copyright © 2005–2013, Texas Instruments Incorporated

Submit Documentation Feedback

19

Product Folder Links: LM2696