FT25H16 datasheet(21/48 Pages) ETC2

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Fremont Micro Devices

Preliminary FT25H16

Confidential Rev1.1

DS25H16-page21

7.9. Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the

capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and

SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit

per clock cycle from SI and SO. The command sequence is shown in followed Figure10. The first byte

addressed can be at any location. The address is automatically incremented to the next higher address after

each byte of data is shifted out. To ensure optimum performance the High Speed mode (HSM) command

(A3H) must be executed once, prior to the Dual I/O Fast Read command.

Dual I/O Fast Read with “Continuous Read Mode”

The Dual I/O Fast Read command can further reduce command overhead through setting the

“Continuous Read Mode” bits (M7- 0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode”

bits (M7-0) =AXH, then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does

not require the BBH command code. The command sequence is shown in followed Figure11. If the

“Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first BBH

command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used

to reset (M7-0) before issuing normal command.

Figure10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

CS#

SCLK

SI(IO0)

SO(IO1)

0 1 2 3 4 5 6 7

BBH

Command

CS#

SCLK

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

12 13 14

8 9 10

20 21 22

16 17 18

A23-16

A15-8

A7-0

M7-0

Byte1

28 29 30

24 25 26

7 5 3 1 7 5 3 1

36 37 38

32 33 34

7 5 3 1 7 5 3 1

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SI(IO0)

SO(IO1)

Byte2

Byte3

Byte4

Byte5

44 45 46

40 41 42

7 5 3 1 7 5 3 1 7

6 4 2 0 6 4 2 0 6

Byte6

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