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MT4LC4M4E8DJS Datasheet(PDF) 9 Page - Micron Technology |
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MT4LC4M4E8DJS Datasheet(HTML) 9 Page - Micron Technology |
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9 / 23 page ![]() 4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 ©1997, Micron Technology, Inc. 9 4 MEG x 4 EDO DRAM TECHNOLOGY, INC. AC ELECTRICAL CHARACTERISTICS (Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX]) AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES OE# setup prior to RAS# during tORD 0 0 ns HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time tPC 20 25 ns EDO-PAGE-MODE READ-WRITE cycle time tPRWC 47 56 ns Access time from RAS# tRAC 50 60 ns 19 RAS# to column address delay time tRAD 9 12 ns 21 Row address hold time tRAH 9 10 ns RAS# pulse width tRAS 50 10,000 60 10,000 ns RAS# pulse width (EDO PAGE MODE) tRASP 50 125,000 60 125,000 ns RAS# pulse width during Self Refresh tRASS 100 100 µs Random READ or WRITE cycle time tRC 84 104 ns RAS# to CAS# delay time tRCD 11 14 ns 22 Read command hold time (referenced to CAS#) tRCH 0 0 ns 23 Read command setup time tRCS 0 0 ns Refresh period (2,048 cycles) tREF 32 32 ms Refresh period (4,096 cycles) tREF 64 64 ms Refresh period S version tREF 128 128 ms RAS# precharge time tRP 30 40 ns RAS# to CAS# precharge time tRPC 5 5 ns RAS# precharge time exiting Self Refresh tRPS 90 105 ns Read command hold time (referenced to RAS#) tRRH 0 0 ns 23 RAS# hold time tRSH 13 15 ns READ WRITE cycle time tRWC 116 140 ns RAS# to WE# delay time tRWD 67 79 ns 13 Write command to RAS# lead time tRWL 13 15 ns Transition time (rise or fall) tT2 50 2 50 ns Write command hold time tWCH 8 10 ns Write command hold time (referenced to RAS#) tWCR 38 45 ns WE# command setup time tWCS 0 0 ns 13 Output disable delay from WE# tWHZ 0 12 0 15 ns Write command pulse width tWP 5 5 ns WE# pulse to disable at CAS# HIGH tWPZ 10 10 ns WE# hold time (CBR Refresh) tWRH 8 10 ns WE# setup time (CBR Refresh) tWRP 8 10 ns |
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