RES

SS1

and

SS2

OUT1

0V

2.55V

5.0V

t1

t2

t3

Current Limit Detected at

CS1 and/or CS2

OUT2

50 2A

1 2A

1.5V

LM5032

SNVS344B – MARCH 2005 – REVISED DECEMBER 2014

www.ti.com

Feature Description (continued)

Figure 17. Current Limit Restart Timing

7.3.8 Soft-Start

Each soft-start circuit allows the corresponding regulator to gradually reach a steady state operating point,

thereby reducing startup current surges and output overshoot. Upon turn-on, both SS pins are internally held at

ground. When VCC increases past its under-voltage threshold (UVT), the SS pins are released and internal 50

µA current sources charge the external capacitors. The voltage at each COMP pin follows the SS pin, and when

COMP reaches

≊1.5V, the output pulses commence at a low duty cycle. The voltage at the SS pins continues to

increase and saturates at

≊5.0V, The voltage at each COMP pin increases to the value required for regulation

where it is controlled by its voltage feedback loop (see Figure 1).

If the internal Drivers Off line is activated (see Drivers Off, VCC Disable), both SS pins are internally grounded.

The SS pins pull the COMP pins to ground while the Driver Off signal disables the output drivers. When the

event which activated the Drivers Off line is cleared and Vcc exceeds its under-voltage threshold, the SS pins

are released. The internal 50 µA current sources then charge the external soft-start capacitors allowing each

regulator’s output duty cycle to increase.

If the Current Limit Restart threshold is reached due to repeated over-current detections, both SS pins (and the

COMP pins) are pulled to ground. The output drivers are disabled, and the 50 µA SS pin current sources are

reduced to 1 µA. After a short propagation delay the SS pins and the COMP pins are released, and the external

capacitors are charged up at a slow rate. When the COMP voltage reaches

≊ 1.5V, the output drivers are

enabled, and the current sources at the SS pins are increased to 50 µA. The output duty cycle then increases to

the value required for regulation.

To shutdown one regulator without affecting the other, ground the appropriate SS pin. This forces the COMP pin

to ground, reducing the output duty cycle to zero for that regulator. Releasing the SS pin allows normal operation

to resume.

7.3.9 Output Duty Cycle

The output driver’s duty cycle for each controller is normally controlled by comparing the voltage provided to the

COMP input by the external voltage feedback circuit with the current information at the CS pin. However, the

maximum duty cycle during transient or fault conditions may be intentionally limited by two other circuits, both of

which are common to the two controller channels.

connected from the DCL pin to GND1, according to the following equation:

(2)

the DCL pin is compared to the Ramp1 and Ramp2 signals, creating the UserMaxDC1 and UserMaxDC2 timing

signals. These signal are provided to the two 4-input AND gates to limit the PWM duty cycle of both channels.

16

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