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ACE721G Datasheet(PDF) 8 Page - ACE Technology Co., LTD. |
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ACE721G Datasheet(HTML) 8 Page - ACE Technology Co., LTD. |
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8 / 11 page ![]() ACE721G 5V 1A, 1.5MHz Synchronous Buck Converter VER 1.1 8 Soft-start ACE721G Series has a internal soft-start circuitry to reduce supply inrush current during startup conditions. When the device exits under-voltage lockout (UVLO), shutdown mode, or restarts following a thermal-overload event, the l soft-start circuitry slowly ramps up current available at SW. UVLO and Thermal Shutdown If IN drops below 2.5V, the UVLO circuit inhibits switching. Once IN rises above 2.5V, the UVLO clears, and the soft-start sequence activates. Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds TJ= +160°C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 15°C, resulting in a pulsed output during continuous overload conditions. Following a thermal-shutdown condition, the soft-start sequence begins. Design Procedure Setting Output Voltages Output voltages are set by external resistors. The FB_ threshold is 0.6V. RTOP = RBOT [(VOUT / 0.6) - 1] Input Capacitor Selection The input capacitor in a DC-to-DC converter reduces current peaks drawn from the battery or other input power source and reduces switching noise in the controller. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source. The output capacitor keeps output ripple small and ensures control-loop stability. The output capacitor must also have low impedance at the switching frequency. Ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest ESR and high-frequency impedance. Output ripple with a ceramic output capacitor is approximately as follows: VRIPPLE = IL(PEAK)[1 / (2 π x f OSC x COUT)] If the capacitor has significant ESR, the output ripple component due to capacitor ESR is as follows: VRIPPLE(ESR) = IL(PEAK) x ESR |
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