MT8972BE datasheet(14/20 Pages) MITEL

14 / 20 page

MT8971B/72B

9-120

Applications

Typical connection diagrams are shown in Figures

13 and 14 for the DN mode as a MASTER and

SLAVE, respectively. LOUT is connected to the

coupling transformer through a resistor R2 and

capacitors

and

C2’

match

the

line

characteristic impedance. Suggested values of R2,

C2 and C2’ for 80 and 160 kbit/s operation are

provided

Figures

and

14.

Overvoltage

protection is provided by R1, D1 and D2. C1 is

present to properly bias the received line signal for

the LIN input. A 2:1 coupling transformer is used to

couple to the line with a secondary center tap for

optional phantom power feed. Varistors have been

shown for surge protection against such things as

lightning strikes.

If the scramblers power up with all zeros in them,

they are not capable of randomizing all-zeros data

sequence. This increases the correlation between

the transmit and receive data which may cause loss

of convergence in the echo canceller and high bit

error rates.

In DN mode the insertion of the SYNC pattern will

provide enough pseudo-random activity to maintain

convergence. In MOD mode the SYNC pattern is not

inserted. For this reason, at least one ”1” must be fed

into the DNIC on power up to ensure that the

scramblers will randomize any subsequent all-zeros

sequence.

Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s

Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s

DV Port ST-BUS

CD Port ST-BUS

Master Clocks

Mode Select

Lines

{

+5V

0.33

µF

0.33

µF

DSTi

DSTo

CDSTi

CDSTo

MS0

MS1

MS2

VRef

VBias

LOUT

LIN

OSC1

OSC2

F0o

D.C. coupled,

Frequency locked

10.24 MHz clock.

R2 = 390

Ω

R1 = 47

Ω

C2’ = 1.5 nF

C2 = 22 nF

+5V

D1 = D2 = MUR405

2 : 1

1.0

µF

Line Feed

Voltage

For 80 kbit/s: C2’ = 3.3 nF

C1 = 0.33

µF

68 Volts

(Typ)

2.5 Joules

0.02 Watt

Note: Low leakage diodes (1 & 2) are required so

that the DC voltage at LIN ≈ VBias

To Next DNIC

MT8971B/72B

Refer to AC Electrical

Characteristics

DN Mode

Clock Timing

DV Port ST-BUS

CD Port ST-BUS

Master Clocks

Mode Select

Lines

+5V

0.33

µF

0.33

µF

DSTi

DSTo

CDSTi

CDSTo

MS0

MS1

MS2

VRef

VBias

LOUT

LIN

OSC1

OSC2

R2 = 390

Ω

R1 = 47

Ω

C2’ = 1.5 nF

C2 = 22 nF

+5V

D1 = D2 = MUR405

2:1

{

1.0

µF

For 80 kbit/s: C2’ = 3.3 nF

C1 = 0.33

µF

68 Volts

(Typ)

0.02 Watt

Note: Low leakage diodes (1 & 2) are required so

2.5 Joules

that the DC voltage at LIN ≈ VBias

10.24 MHz XTAL

C3=33pF=C4

Supply

MT8971B/72B

MT8972BE Datasheet(PDF) 14 Page - Mitel Networks Corporation

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