ISO-CMOS

MT8976

4-49

† Timing is over recommended temperature & power supply voltage ranges.

‡ Typical figures are at 25

°C and are for design aid only; not guaranteed and not subject to production testing

.

Parameters

Sym

Min

Max

Units

Test Conditions

1

External Control Delay

140

ns

50 pF Load

2

External Status Setup Time

100

ns

3

External Status Hold Time

400

ns

4

8 kHz Output Delay

150

ns

50 pF Load

5

8 kHz Output Low Width

78

µs

50 pF Load

6

8 kHz Output High Width

47

µs

50 pF Load

7

8 kHz Rise Time

10

ns

50 pF Load

8

8 kHz Fall Time

10

ns

50 pF Load

Figure 16 - XCtl Timing

ST-BUS Bit Cell Boundary Between

Bit 0 Channel 15 and Bit 7 Channel 16

C2i

2.0V

0.8V

XCtl

2.4V

0.4V

Figure 17 - XSt Timing

ST-BUS Bit Cell Boundary Between

Bit 2 Channel 30 and Bit 1 Channel 30

C2i

XSt

2.0V

0.8V

2.0V

0.8V

Figure 18 - E8Ko Timing

Channel 2

Bit 1

Channel 17

Bit 2

Channel 2

Bit 1

Received

DS1 Bits

E1.5i

2.0V

0.8V

E8Ko

2.4V

0.4V

•• •

•• •