SM5852CS

NIPPON PRECISION CIRCUITS—16

INPUT/OUTPUT TIMING

Input Timing

There must be a minimum of 16 BCKI clock cycles to read in a single word of data.

Data on DI is input in sync with the falling edge of BCKI in 16-bit serial, MSB first, 2s complement

format.

Output Timing

Shaded areas represent intervals of invalid data.

BCKO

LRCO

DOUT

MSB

MSB

Lch

LSB

Rch

LSB

,

,

,,

,,

,

,

BCKI

LRCI

DI

MSB

MSB

Lch

LSB

Rch

LSB