2-106

Figure 4 - Data Memory Mode Functional Timing

Figure 5 - Throughput Delay in Data Memory Mode-1

CK

External

Address

Bus A0-A15

Data Output

D0-D15o

FP

Address

generated by

Internal 11

Bit Counter

Data Input

D0-D15i

CH X

CH Y

CH Z

1022

1023

0

1

2

1

0

1023

Counter Reset

CH X

CH Y

CH Z

PWP

R

Œy

P = Precharge

R = Read Memory

W = Write Memory

Data is clocked out of the memory location addressed by external address bus. The address is latched in with CK edge

marked Œ. Data is clocked out with CK edge marked y.

Data is latched into the device with the last rising edge of CK in the timeslot (e.g., edge Ž in diagram). It is stored in the

Ž

memory location address by the internal 11 bit counter with the next rising clock edge (edge  in diagram).

CK

PW

R

Œy

P

1

4

12

3

4

5

2

3

P = Precharge

R = Read Memory

W = Write Memory

Data on the input bus of the SMX is latched into the device with last rising edge of the clock within a timeslot. It is

Data is clocked out of the memory location and latched onto the output data bus with first positive clock edge in the

Input

Data

Output

Timeslots

written into the internal memory with the following positive edge.

timeslot.

Switching channel 1 to channel 1 or channel 2 will result in one frame delay. Note that channel 2 is clocked out by CK

edge labelled Πwhile channel 1 is written into the memory with edge y. However, if channel 1 is switched to channel

3, there will be only one channel delay.