PDSP16256AC datasheet(10/28 Pages) MITEL

10 / 28 page

PDSP16256

Filter Accuary

Input data and coefficients are both represented by 16-

bit two’s complement numbers. The coefficients are

converted to twelve bits by rounding towards zero. This

is achieved as follows. If the coefficient is positive then

the least significant 4 bits are discarded. If the coefficient

is negative then the logical ‘OR’ of the least significant 4

bits are added to the remainder of the word. Twelve bit

coefficients can be used directly provided the least

significant four bits are set to zero.

The FIR filter results are calculated using a multiplier

accumulator structure as shown in Fig. 10. The trunca-

tion and word growth allowed for in the data path are

explained in Fig. 10. The 16-bit data and 12-bit coeffi-

cient inputs (each with one sign bit before the binary

point), are presented to the multiplier. This produces a

28-bit result with two bits before the binary point. Produc-

ing the full 28-bit result ensures that if both the data and

coefficients are set to logic 1 a valid result is generated.

Prior to entering the accumulator the least significant 4

bits of the multiplier result are truncated and the resulting

24 bits sign extended to 32 bits. The final accumulator

result is 32 bits with 10 bits before the binary point. Thus

9 bits of word growth are allowed within the accumulator.

All accumulator bits are made available on the output

pins.

In cascade mode the middle 16 bits from the network A

accumulator are fed round to the network B data inputs,

see Fig. 11.

COEFFICIENT

ADDER

INPUT DATA

ACCUMULATOR

RESULT

-26

ACCUMULATOR RESULT

These bits are passed to filter network B during cascade mode

-25

-24

-23

-22

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

-22

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

-22

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

-15

ACCUMULATOR RESULT

MULTIPLIER RESULT

COEFFICIENT

INPUT DATA

Sign extended to 32 bits, least significant 4 bits truncated

Multiplication producing a 28-bit result

Figure. 10 Multiplier Accumulator

Figure. 11 Filter accuracy

PDSP16256AC Datasheet(PDF) 10 Page - Mitel Networks Corporation

PDSP16256AC Datasheet(HTML) 10 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL