PDSP16116

7

Shifter

Each of the two adder/subtractors are followed by shifters

controlled via the WTB control input. These shifters can each

apply two different shifts; however, the same shift is applied to

both real and imaginary components. The four shift options are:

1. WTB1:0 = 11 Shift complex product one place to the left, giving a shifter output format:

Bit Number

30

Weighting

29 28 27 26

76543210

S

2

2

2

2

2

2

2

2

2

2

2

31

25

2

2

Bit Number

30

Weighting

29 28 27 26

76543210

S

2

2

2

2

2

2

2

2

2

2

2

0

31

2

8

2

2. WTB1:0 = 00 No shift applied, giving a shifter output format:

Bit Number

30

Weighting

29 28 27 26

6543210

S

2

2

2

2

2

2

2

2

2

2

0

31

2

2

2

1

25

2

24

4. WTB1:0 = 10 Shift complex product two places to the right, giving a shifter output format:

Bit Number

30

Weighting

29 28 27 26

6543210

S

2

2

2

2

2

2

2

2

2

0

31

2

2

2

1

25 24

2

2

2

3. WTB1:0 = 01 Shift complex product one place to the right, giving a shifter output format:

PIN DESCRIPTIONS

XR, XI, YR, YI

Data inputs, 16 bits. Data is loaded into the input registers

from these ports on the rising edge of CLK. The data format is

fractional two’s complement, where the MSB (sign bit) is bit 15.

PR, PI

Data outputs, 16 bits. Data is clocked into the output regis-

ters and passed to the PR and PI outputs on the rising edge of

CLK. The data format is fractional two’s complement. The field

of the internal result selected for output via PR and PI is control-

led by signals OSEL1:0 (see Table 4).

CLK

Common clock to all internal registers

Clock enables for X and Y input ports. When low these inputs

enable the CLK signal to the X or Y input registers, allowing

new data to be clocked into the Multiplier.

CONX, CONY

Conjugate controls. If either of these inputs is high on the

rising edge of CLK, then the data on the associated input has its

imaginary component inverted (multiplied by 21), see Table 3.

CONX and CONY affect data input on the same clock rising

edge.

ROUND

The ROUND control pin is used to round the most significant 16

bits of the output register. The ROUND input is not latched and is

intended to be tied high or low depending upon the application.

MSR and LSR are the most and least siginificant 16-bit words

of the real shifter output, MSl and LSl are the most and least

significant 16-bit words of the imaginary shifter output.

The output select options allow two different modes for ex-

tracting the full 32-bit result from the PDSP16116. The first mode

treats the two 16-bit outputs as real and imaginary ports, allow-

ing the real and imaginary results to be output in two halves on

the real and imaginary output ports. The second mode treats

the two 16-bit outputs as one 32-bit output and allows the real

and imaginary results to be output as 32-bit words.

Table 4 Output selection

Overflow

If the left shift option is selected and the adder/subtractor

contains a 32-bit word, then an invalid result will be passed to

the output. An invalid output arising from this combination of

events will be flagged by the SFTA0 flag output. The SFTA0 flag

will go high if either the real or imaginary result is invalid.

Output Select

The output from the shifters is passed to the output select

mux, which is controlled via the OSEL inputs. These inputs are

not registered and hence allow the output combination to be

changed within each cycle. The full complex 64-bit result from

the multiplier may therefore be output within a single cycle. The

OSEL control selects four different output combinations as

summarised in Table 4.

OSEL1

0

1

0

1

P1

PR

OSEL0

MSR

LSR

MSR

MSI

0

0

1

1

MSI

LSI

LSR

LSI

CEX, CEY