SP8858IGHPAS datasheet(3/17 Pages) MITEL

3 / 17 page

SP8858

Fig. 2 SP8858 block diagram

FREQUENCY (MHz)

500

400

300

200

100

500

750

1000

1500

TYPICAL

SENSITIVITY

GUARANTEED

OPERATING

WINDOW

48/9 MODE

GUARANTEED

OPERATING

WINDOW

416/17 MODE

Fig. 3 Typical input characteristics and input drive requirements

fPD

COUNTER

F1/F2 22-BIT DATA BUFFER

COUNTER

24-BIT SHIFT REGISTER

16-BIT REFERENCE BUFFER

DATA

INTERFACE

16/17 OR 8/9

PHASE

DETECTOR

DIVIDER

BUFFER

LOCK

DETECT

RF INPUT

F1/F2

DATA

CLOCK

ENABLE

POWER

DOWN

RPD

CP OUTPUT

CRYSTAL

FREF*

FPD*

*FREF and FPD outputs are reversed by the phase detector

sense bit in the F1/F2 programming word. The pin allocations

shown are correct when the sense bit is low (see Fig. 6).

RF INPUT

C1 C2

XFV

RESET

15 BITS

4 BITS

3 BITS

SELECT F1/F2

ACTIVE A

LSB

MSB

22 BITS

SELECT MODULUS

16 BITS

SELECT R

VREF

13 BITS

PD GAIN

2 BITS

XFR

DECODE

PD1

PD2

XFV

XFR

CHARGE

PUMP

SENSE

DISABLE

CP REF

LOCK

DETECT

MODULUS CONTROL

SP8858IGHPAS Datasheet(PDF) 3 Page - Mitel Networks Corporation

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