VP306 datasheet(20/85 Pages) MITEL

20 / 85 page

VP305/6

DRAFT - PRELIMINARY DATA

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

2.1. Parallel interface register map.

The default state of almost all of the registers is zero, except the ID register and unused registers.

Reserved or unused bits should be set to zero when writing to a register.

NAME

ADR

D7D6D5D4D3D2

D1D0

R/W

BANK

Reserved

AD5

AD4

AD3

Reserved

Table 5a. BANK Register 0. (Address byte = 0, Data byte = NEXT BANK)

NAME

ADR

D7D6D5D4D3D2

D1D0

R/W

ID[7:0] Chip identification

INT_QPSK

INT_QPSK[7:0] Interrupt QPSK

INT_FEC

INT_FEC[7:0] Interrupt FEC

STATUS

Reserved

STATUS[6:0]

AGC_LVL

AGC_LVL[7:0] AGC loop voltage meter

CR_VCOF U

Reserved

CR_VCOF[13:8] Measured VCO frequency (upper nibble)

CR_VCOF L

CR_VCOF[7:0] Measured VCO frequency (lower byte)

IE_QPSK

IE_QPSK[7:0] Interrupt enable QPSK

R/W

Table 5b. Register bank 0. BANK[5:3] = 0.

Note: In Bank 0, the registers 1 to 6 are READ only. Writing to these addresses will have no

effect.

NAME

ADR

D7D6D5D4D3D2

D1D0

R/W

ID[7:0] Chip identification

SYM_CONFIG

Reserved

SYM_CONFIG[5:0] Symbol configuration

R/W

SYM_RP

Reserved

SYM_RP[3:0] Symbol AFC reference

period

R/W

SYM_NF U

SYM_NF[15:8] Symbol input nominal frequency (upper byte)

R/W

SYM_NF L

SYM_NF[7:0] Symbol input nominal frequency (lower byte)

R/W

SYM_RATIO

Reserved

SYM_RATIO[2:0]

R/W

AGC_REF

AGC_REF[7:0] Reference AGC level

R/W

AGC_BW

Reserved

INT_DC

AGC_BW[2:0]

R/W

Table 5c. Register bank 1. BANK[5:3] = 8.

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