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Z86C9524ASC Datasheet(PDF) 11 Page - Zilog, Inc.

Part # Z86C9524ASC
Description  CMOS Z8 DIGITAL SIGNAL PROCESSOR (DSP)
PDF  18 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C9524ASC Datasheet(HTML) 11 Page - Zilog, Inc.

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Z86C95 DSP
CPS DC-4067-13
AC CHARACTERISTICS
External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table
T
A = 0°C to +70°C
40 MHz**
33 MHz
24 MHz
No
Sym
Parameter
Min
Max
Min
Max
Min
Max
Units
1
TdA(AS)
Address Valid To /AS Rise Delay
8
15
22
ns
2
TdAS(A)
/AS Rise To Address Hold Time
15
20
25
ns
3
TdAS(DI)
/AS Rise Data In Req’d Valid Delay
75
96
130
ns
4
TwAS
/AS Low Width
10
15
28
ns
5
TdAZ(DSR)
Address Float To /DS Fall (Read)
0
0
0
ns
6
TwDSR
/DS (Read) Low Width
60
65
100
ns
7
TwDSW
/DS (Write) Low Width
35
40
65
ns
8
TdDSR(DI)
/DS Fall (Read) To Data Req'd Valid Delay
40
45
80
ns
9
ThDSR(DI)
/DS Rise (Read) to Data In Hold Time
0
0
0
ns
10
TdDS(A)
/DS Rise To Address Active Delay
20
25
40
ns
11
TdDS(AS)
/DS Rise To /AS Delay
16
16
30
ns
12
TdR/W(AS)
R/W To Valid /AS Rise Delay
10
12
26
ns
13
TdDS(R/W)
/DS Rise To R/W Not Valid Delay
12
12
30
ns
14
TdDO(DSW)
Data Out To /DS Fall (Write) Delay
12
12
34
ns
15
ThDSW(DO)
/DS Rise (Write) To Data Out Hold Time
12
12
34
ns
16
TdA(DI)
Address Valid To Data Req’d Valid Delay
90
115
160
ns
17
TdAS(DSR)
/AS Rise To /DS Fall (Read) Delay
20
20
40
ns
19
TdDM(AS)
/DM Valid To /AS Rise Delay
10
10
22
ns
20
TdDS(DM)
/DS Rise To /DM Valid Delay
15
15
35
ns
21
ThDS(A)
/DS Rise To Address Valid Hold Time
15
15
30
ns
22
TdXT(SCR)
XTAL Falling to SCLK Rising
30
35
40
ns
23
TdXT(SCF)
XTAL Falling to SCLK Falling
30
35
40
ns
24
TdXT(DSRF)
XTAL Falling to/DS Read Falling
40
45
50
ns
25
TdXT(DSRR)
XTAL Falling to /DS Read Rising
30
35
45
ns
26
TdXT(DSWF)
XTAL Falling to /DS Write Falling
40
45
50
ns
27
TdXT(DSWF)
XTAL Falling to /DS Write Rising
30
35
45
ns
28
TsW(XT)
Wait Set-up Time
5
5
5
ns
29
ThW(XT)
Wait Hold Time
15
15
15
ns
30
TwW
Wait Width (One Wait Time)
20
20
25
ns
Notes:
When using extended memory timing add 2 TpC.
Timing numbers given are for minimum TpC.
** Preliminary values, to be characterized.



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