Z86C9620VSC datasheet(17/46 Pages) ZILOG

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Z86C61/62/96

Z8® MICROCONTROLLER

Port 3 can be configured under software control to provide

the following control functions: handshake for Ports 0 and

2 (/DAV and RDY); four external interrupt request signals

(IRQ3-IRQ0); timer input and output signals (T

IN and TOUT),

and Data Memory Select (/DM).

Start Bit

Eight Data Bits

Transmitted Data (No Parity)

Two Stop Bits

SP SP

Start Bit

Eight Data Bits

Received Data (No Parity)

One Stop Bit

D6D5D4D3D2D1D0

Start Bit

Seven Data Bits

Transmitted Data (With Parity)

Odd Parity

Two Stop Bits

SP SP

D6D5D4D3D2D1D0

Start Bit

Seven Data Bits

Received Data (With Parity)

Parity Error Flag

One Stop Bit

Figure 14. Serial Data Formats

Table 7. Port 3 Pin Assignments

I/O

CTC1

Int.

P0 HS

P1 HS

P2 HS

UART

Ext

P30

IRQ3

Serial In

P31

IRQ2

D/R

P32

IRQ0

D/R

P33

IRQ1

D/R

P34

OUT

R/D

P35

OUT

R/D

P36

OUT

R/D

P37

OUT

Serial Out

IRQ4

IRQ5

Notes:

HS = Handshake Signals

D = Data Available

R = Ready

UART OPERATION

Port 3 lines P30 and P37, can be programmed as serial

I/O lines for full-duplex serial asynchronous receiver/

transmitter operation. The bit rate is controlled by the

Counter/Timer0.

The Z86C61/62/96 automatically adds a start bit and two

stop bits to transmitted data (Figure 14). Odd parity is also

available as an option. Eight data bits are always transmit-

ted, regardless of parity selection. If parity is enabled, the

eighth bit is the odd parity bit. An interrupt request (IRQ4)

is generated on all transmitted characters.

Received data must have a start bit, eight data bits and at

least one stop bit. If parity is on, bit 7 of the received data

is replaced by a parity error flag. Received characters

generate the IRQ3 interrupt request.

Note: UART function is only available in stardard timing

mode (i.e., P01M D5 = 0).

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