Z86L0808PSC datasheet(18/26 Pages) ZILOG

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Z86L04/L08

Z8 8-Bit Cost-Effective Microcontrollers

Zilog

P R E L I M I N A R Y

DS97LVO0901

FUNCTIONAL DESCRIPTION (Continued)

Interrupts. The Z8 has five interrupts from four different

sources. These interrupts are maskable and prioritized

(Figure 15). The sources are divided as follows: the falling

edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge

of P32 (AN2), and one counter/timer. The Interrupt Mask

five interrupt requests (Table 4).

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder that is con-

trolled by the Interrupt Priority register. All Z8 interrupts are

vectored through locations in program memory. When an

Interrupt machine cycle is activated, an Interrupt Request

is granted. This disables all subsequent interrupts, saves

the Program Counter and Status Flags, and then branches

to the program memory vector location reserved for that in-

terrupt. This memory location and the next byte contain the

16-bit starting address of the interrupt service routine for

that particular interrupt request.

To accommodate polled interrupt systems, interrupt inputs

are masked and the interrupt request register is polled to

determine which of the interrupt requests needs service.

User must select any Z86E08 mode in Zilog's C12 ICE-

BOX™ emulator. The rising edge interrupt is not directly

supported on the Z86CCP00ZEM emulator.

Table 4. Interrupt Types, Sources, and Vectors

Vector

Name

Source

Location

Comments

IRQ0

AN2(P32)

0,1

External (F)Edge

IRQ1

REF(P33)

2,3

External (F)Edge

IRQ2

AN1(P31)

4,5

External (F)Edge

IRQ3

AN2(P32)

6,7

External (R)Edge

IRQ4

8,9

Internal

IRQ5

10,11

Internal

Note:

F = Falling edge triggered

R = Rising edge triggered

Figure 15. Interrupt Block Diagram

IRQ0 - IRQ5

IRQ

IMR

IPR

Priority

Logic

Global

Interrupt

Enable

Vector Select

Interrupt

Request

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