AX88140AP datasheet(15/46 Pages) ASIX

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AX88140A

PRELIMINARY

ASIX ELECTRONICS CORPORATION

MRCLK/SYMRCLK

128

114

Supports either the 25-MHZ or 2.5-MHZ receive

clock. This clock is recovered by the PHY.

MRXD<3>/SYMRXD<3>

MRXD<2>/SYMRXD<2>

MRXD<1>/SYMRXD<1>

MRXD<0>/SYMRXD<0>

132,

131,

130,

129

118,

117,

116,

115

Four parallel receive data lines When MII mode is

selected. This data is driven by an external PHY that

attached the media and should be synchronized with

the MRCLK/SYMRCLK signal.

MTCLK/SYMTCLK

137

123

Supports the 25-MHZ or 2.5-MHZ transmit clock

supplied by the external physical layer medium

dependent (PMD) device. This clock should always

be active.

MTXD<3>/SYMTXD<3>

MTXD<2>/SYMTXD<2>

MTXD<1>/SYMTXD<1>

MTXD<0>/SYMTXD<0>

145,

144,

141,

140

131,

130,

127,

126

Four parallel transmit data lines. This data is

synchronized to the assertion of the

MTCLK/SYMTCLK signal and is latched by the

external PHY on the rising edge of the

MTCLK/SYMTCLK signal.

MTXEN/SYMTXEN

139

125

Transmit enable signals that the transmit is active to

an external PHY device. In PCS mode (REG6<23>),

This signal reflects the transmit activity of the MAC

sub-layer.

RCV_MATCH

136

122

Receive match indication is asserted when a received

packet has passed address recognition.

Receive match indication is asserted when a received

packet has passed address recognition.

123

109

Signal detect indication supplied by an external

physical layer medium dependent (PMD) device.

SRL_CLSN

148

134

Collision detect signals a collision occurrence on the

Ethernet cable to the AX88140A. It may be asserted

and deasserted asynchronously by the external

ENDEC to the receive clock.

SRL_RCLK

151

137

Receive clock carries the recovered receive clock

supplied by an external ENDEC. during idle periods,

SRL_RCLK may be inactive.

SRL_RXD

149

135

Receive data carries the input receive data from the

external ENDEC. The incoming data should be

synchronous with the SRL_RCLK signal.

SRL_RXEN

150

136

Receive enable signals activity on the Ethernet cable

to the AX88140A. It is asserted when receive data is

present on the Ethernet cable and is deasserted at the

end of a frame. It may be asserted and deasserted

asynchronously to the receive clock (SRL_RCLK) by

the external ENDEC.

SRL_TCLK

153

139

Transmit clock carries the transmit clock supplied by

an external ENDEC. This clock must always be

active (even during reset).

SRL_TXD

152

138

Transmit data carries the serial output data from the

AX88140A. This data is synchronized to the

SRL_TCLK signal.

SRL_TXEN

154

140

Transmit enable signals an external ENDEC That the

AX88140A transmit is in progress.

SYMRXD <4>

133

119

Receive data, together with the four receive lines

MII/SYM_RXD<3:0>, Provide five parallel lines of

data in symbol from for use in PCS mode

(100BASE-T, REG6<23). This data is synchronized

on the rising edge of the MTCLK/SYMTCLK signal.

SYMTXD<4>

146

132

Transmit data, together with the our transmit lines

MII/SYM_TXD<3:0>,provide five parallel lines of

data in symbol form for use in PCS mode

(100BASE-T, REG6<23>). This data is synchronized

on the rising edge of the MII/SYM_TCLK signal.

Tab - 3 MII/SYM/SRL interface signals group

AX88140AP Datasheet(PDF) 15 Page - ASIX Electronics Corporation

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