AX88196 datasheet(11/42 Pages) ASIX

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AX88196

Local CPU BUS MAC Controller

ASIX ELECTRONICS CORPORATION

AEN

/PSEN

I/PD

124

Address Enable : The signal is asserted when the address bus is

available for DMA cycle. When negated (low), AX88196 an I/O slave

device may respond to addresses and I/O command.

PSEN : This signal is active low for 8051 program access. For I/O

device, AX88196, this signal is active high to access the chip. This

signal is for 8051 bus application only.

Tab - 1 Local CPU bus interface signals group

2.2 MII interface signals group

SIGNAL

TYPE

PIN NO.

DESCRIPTION

RXD[3:0]

90 – 87

Receive Data : RXD[3:0] is driven by the PHY synchronously with

respect to RX_CLK.

CRS

Carrier Sense : Asynchronous signal CRS is asserted by the PHY

when either the transmit or receive medium is non-idle.

RX_DV

Receive Data Valid : RX_DV is driven by the PHY synchronously

with respect to RX_CLK. Asserted high when valid data is present on

RXD [3:0].

RX_ER

Receive Error : RX_ER ,is driven by PHY and synchronous to

RX_CLK, is asserted for one or more RX_CLK periods to indicate to

the port that an error has detected.

RX_CLK

Receive Clock : RX_CLK is a continuous clock that provides the

timing reference for the transfer of the RX_DV,RXD[3:0] and

RX_ER signals from the PHY to the MII port of the repeater.

COL

Collision : this signal is driven by PHY when collision is detected.

TX_EN

Transmit Enable : TX_EN is transition synchronously with respect to

the rising edge of TX_CLK. TX_EN indicates that the port is

presenting nibbles on TXD [3:0] for transmission.

TXD[3:0]

99 – 96

Transmit Data : TXD[3:0] is transition synchronously with respect to

the rising edge of TX_CLK. For each TX_CLK period in which

TX_EN is asserted, TXD[3:0] are accepted for transmission by the

PHY.

TX_CLK

Transmit Clock : TX_CLK is a continuous clock from PHY. It

provides the timing reference for the transfer of the TX_EN and

TXD[3:0] signals from the MII port to the PHY.

MDC

Station Management Data Clock : The timing reference for MDIO.

All data transfers on MDIO are synchronized to the rising edge of this

clock. MDC is a 2.5MHz frequency clock output.

MDIO

I/O/PU

Station Management Data Input / Output : Serial data input/output

transfers from/to the PHYs . The transfer protocol conforms to the

IEEE 802.3u MII specification.

Tab - 2 MII interface signals group

AX88196 Datasheet(PDF) 11 Page - ASIX Electronics Corporation

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