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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 17 of 62
3.3V AC Test Loads and Waveforms
AC Characteristics
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
<2 ns
OUTPUT
295
Ω (COM’L)
393
Ω (MIL)
340
Ω (COM’L)
453
Ω (MIL)
Equivalent to:
THÉVENIN EQUIVALENT
1.77V (COM'L)
1.77V (MIL)
295
Ω (COM'L)
393
Ω (MIL)
340
Ω (COM'L)
453
Ω (MIL)
<2 ns
(c)
270
Ω (MIL)
158
Ω (COM’L)
5 OR 35 pF
Parameter[11]
VX
Output Waveform—Measurement Level
tER(–)
1.5V
tER(+)
2.6V
tEA(+)
1.5V
tEA(–)
Vthe
(d) Test Waveforms
VOH
VX
0.5V
VOL
VX
0.5V
VX
VOH
0.5V
VX
VOL
0.5V
Switching Characteristics Over the Operating Range[12]
Parameter
Description
Unit
Combinatorial Mode Parameters
tPD
[13, 14, 15]
Input to Combinatorial Output
ns
tPDL
[13, 14, 15]
Input to Output Through Transparent Input or Output Latch
ns
tPDLL
[13, 14, 15]
Input to Output Through Transparent Input and Output Latches
ns
tEA
[13, 14, 15]
Input to Output Enable
ns
tER
[11, 13]
Input to Output Disable
ns
Input Register Parameters
tWL
Clock or Latch Enable Input LOW Time[8]
ns
Notes:
11.
tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add tLP to this spec.
14. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
15. When VCCO = 3.3V, add t3.3IO to this spec.
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