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REF5030IDGKT Datasheet(PDF) 19 Page - Texas Instruments |
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REF5030IDGKT Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 38 page ![]() ADS8326 REF5040 OPA365 ESR 47µF 10µF REFIN CS CLK SDO 1nF 0-4V 124 Ÿ REF5010, REF5020, REF5025, REF5030 REF5040, REF5045, REF5050 www.ti.com SBOS410G – JUNE 2007 – REVISED NOVEMBER 2015 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information Data acquisition systems often require stable voltage references to maintain accuracy. The REF50xx family features low noise, very low drift, and high initial accuracy for high-performance data converters. Figure 42 shows the REF5040 in a basic data acquisition system. 10.2 Typical Applications 10.2.1 16-bit, 250-KSPS Data Acquisition System Figure 42. Complete Data Acquisition System Using REF50xx 10.2.1.1 Design Requirements When using REF50xx in the design, it is important to select proper output capacitor that does not create gain peaking which increases total system noise. At the same time, the capacitor must be selected to provide required filtering performance for the system. In addition, input bypass capacitor and noise reduction capacitors must be added for optimum performances. During the design of the data acquisition system, equal consideration must be given to the buffering analog input signal as well as the reference voltage. Having a properly designed input buffer with an associated RC filter is a necessary requirement for good performance of the Data Acquisition System. 10.2.1.2 Detailed Design Procedure The OPA365 is used to drive the 16-bit Analog to Digital Converter (ADS8326). The RC filter at the output of the OPA365 is used to reduce the charge kick-back created by the opening and closing of the sampling switch inside the ADC. The RC filter should be designed such that the voltage at the sampling capacitor settles to 16-bit accuracy within the acquisition time of the ADC. The bandwidth of the driving amplifier should at least be 4 times the bandwidth of the RC filter. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: REF5010 REF5020 REF5025 REF5030 REF5040 REF5045 REF5050 |
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