AS3630 datasheet(40/72 Pages) AMSCO

40 / 72 page

AS3630 – 40

8A Supercap Flash Driver

Start Data Transfer

A change in the state of the data line, from HIGH to LOW, while

the clock is HIGH, defines a START condition.

Stop Data Transfer

A change in the state of the data line, from LOW to HIGH, while

the clock line is HIGH, defines the STOP condition.

Data Valid

The state of the data line represents valid data when, after a

START condition, the data line is stable for the duration of the

HIGH period of the clock signal. The data on the line must be

changed during the LOW period of the clock signal. There is one

clock pulse per bit of data.

Each data transfer is initiated with a START condition and

terminated with a STOP condition. The number of data bytes

transferred between START and STOP conditions are not

limited, and are determined by the master device. The

information is transferred byte-wise and each receiver

acknowledges with a ninth bit.

Acknowledge

Each receiving device, when addressed, is obliged to generate

an acknowledge after the reception of each byte. The master

device must generate an extra clock pulse that is associated

with this acknowledge bit.

A device that acknowledges must pull down the SDA line during

the acknowledge clock pulse in such a way that the SDA line is

stable LOW during the HIGH period of the acknowledge-related

clock pulse. Of course, setup and hold times must be taken into

account. A master must signal an end of data to the slave by not

generating an acknowledge bit on the last byte that has been

clocked out of the slave. In this case, the slave must leave the

data line HIGH to enable the master to generate the STOP

condition.

AS3630 Datasheet(PDF) 40 Page - ams AG