LMK03328 datasheet(2/153 Pages) TI1

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LMK03328

SNAS668A – AUGUST 2015 – REVISED JANUARY 2016

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Table of Contents

Features .................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description Continued .......................................... 3

Device Comparison Table..................................... 3

Pin Configuration and Functions ......................... 4

Specifications......................................................... 6

8.1

Absolute Maximum Ratings ...................................... 6

8.2

ESD Ratings.............................................................. 6

8.3

Recommended Operating Conditions ....................... 6

8.4

Thermal Information .................................................. 7

8.5

Thermal Information .................................................. 7

8.6

Electrical Characteristics - Power Supply ................ 7

8.7

Pullable Crystal Characteristics (SECREF_P,

SECREF_N)............................................................... 9

8.8

Non-Pullable Crystal Characteristics (SECREF_P,

SECREF_N)............................................................. 10

8.9

Clock Input Characteristics (PRIREF_P/PRIREF_N,

SECREF_P/SECREF_N)......................................... 10

8.10

VCO Characteristics.............................................. 10

8.11

PLL Characteristics ............................................... 11

8.12

1.8-V LVCMOS Output Characteristics

(OUT[7:0]) ................................................................ 11

8.13

LVCMOS Output Characteristics (STATUS[1:0]... 11

8.14

Open-Drain Output Characteristics

(STATUS[1:0]).......................................................... 12

8.15

AC-LVPECL Output Characteristics ..................... 12

8.16

AC-LVDS Output Characteristics .......................... 12

8.17

AC-CML Output Characteristics............................ 13

8.18

HCSL Output Characteristics ................................ 13

8.19

Power-On/Reset Characteristics........................... 13

8.20

2-Level Logic Input Characteristics

(HW_SW_CTRL, PDN, GPIO[5:0]).......................... 14

8.21

3-Level Logic Input Characteristics (REFSEL,

GPIO[3:1]) ................................................................ 14

8.22

Analog Input Characteristics (GPIO[5])................. 14

8.23

I2C-Compatible Interface Characteristics (SDA,

SCL) ......................................................................... 15

8.24

Typical 156.25 MHz Closed Loop Output Phase

Noise Characteristics ............................................... 15

8.25

Typical 161.1328125 MHz Closed Loop Output

Phase Noise Characteristics.................................... 16

8.26

Closed Loop Output Jitter Characteristics ............ 16

8.27

Typical Power Supply Noise Rejection

Characteristics ......................................................... 17

8.28

Typical Power Supply Noise Rejection

Characteristics ......................................................... 17

8.29

Typical Closed Loop Output Spur Characteristics 18

8.30

Typical Performance Characteristics .................... 19

Parameter Measurement Information ................ 23

9.1

Test Configurations ................................................. 23

Detailed Description ........................................... 27

10.1

Overview ............................................................... 27

10.2

Functional Block Diagram ..................................... 27

10.3

Feature Description............................................... 28

10.4

Device Functional Modes...................................... 32

10.5

Programming......................................................... 50

10.6

10.7

EEPROM Map..................................................... 122

Application and Implementation...................... 128

11.1

Application Information........................................ 128

11.2

Typical Applications ............................................ 128

Power Supply Recommendations ................... 139

12.1

Device Power Up Sequence ............................... 139

12.2

Device Power Up Timing .................................... 140

12.3

Power Down........................................................ 141

12.4

Power Rail Sequencing, Power Supply Ramp Rate,

and Mixing Supply Domains .................................. 141

12.5

Power Supply Bypassing .................................... 143

Layout................................................................. 144

13.1

Layout Guidelines ............................................... 144

Device and Documentation Support ............... 146

14.1

Community Resources........................................ 146

14.2

Trademarks ......................................................... 146

14.3

Electrostatic Discharge Caution .......................... 146

14.4

Glossary .............................................................. 146

Mechanical, Packaging, and Orderable

Information ......................................................... 147

4 Revision History

Changes from Original (August 2015) to Revision A

Page

•

Changed title from Configuring PLL1 and PLL2 to Device Functional Modes ..................................................................... 32

•

Changed title from Interface and Control to Programming .................................................................................................. 50

•

Added new sections to Power Supply Recommendations ................................................................................................ 141

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