Data Sheet

ADA4806-1

Figure 61 shows a typical 16-bit, single-supply application. The

ADA4806-1 drives the AD7980, a 16-bit, 1 MSPS, SAR ADC in

a low power configuration. The AD7980 operates on a 2.5 V

ADR435 provides a 5 V reference. The ADA4806-1 is used both

as a driver for the AD7980 and as a reference buffer for the

ADR435.

The low-pass filter formed by R3 and C1 reduces the noise to

the input of the ADC (see Figure 61). In lower frequency

applications, the designer can reduce the corner frequency of

the filter to remove additional noise.

AD7980

C2

10µF

IN+

IN–

GND

VDD

REF

C3

0.1µF

C4

100nF

VDD

C1

2.7nF

R3

20Ω

+7.5V

+7.5V

ADA4806-1

ADA4806-1

ADR435

5V REF

0V TO

Figure 61. Driving the AD7980 with the ADA4806-1

In this configuration, the ADA4806-1 consume 7.2 mW of

quiescent power. The measured signal-to-noise ratio (SNR),

THD, and signal-to-noise-and-distortion ratio (SINAD) of the

whole system for a 10 kHz signal are 89.4 dB, 104 dBc, and

89.3 dB, respectively. This translates to an effective number of

bits (ENOB) of 14.5 at 10 kHz, which is compatible with the

AD7980 performance. Table 10 shows the performance of this

setup at selected input frequencies.

DYNAMIC POWER SCALING

One of the merits of a SAR ADC, like the AD7980, is that its

power scales with the sampling rate. This power scaling makes

SAR ADCs very power efficient, especially when running at a

low sampling frequency. However, the ADC driver used with

the SAR ADC traditionally consumes constant power regardless

of the sampling frequency.

Figure 62 illustrates a method by which the quiescent power of

the ADC driver can be dynamically scaled with the sampling

rate of the system. By providing properly timed signals to the

convert input (CNV) pin of the ADC and the SHUTDOWN

and SLEEP pins of the ADA4806-1, both devices can be run at

optimum efficiency.

+5V

2.7nF

20Ω

TIMING

GENERATOR

AD7980

ADA4806-1

REF

VDD

GND

+6V

+2.5V

0.1µF

CNV

Figure 62. ADA4806-1/AD7980 Power Management Circuitry

Figure 63 illustrates the relative signal timing for power scaling

the ADA4806-1 and the AD7980. To prevent any degradation in

the performance of the ADC, the ADA4806-1 must have a fully

settled output into the ADC before the activation of the

is enabled prior to the rising edge of the CNV signal; this time

depends on whether the SHUTDOWN pin or SLEEP pin is being

SHUTDOWN pin and 0.5 µs for the SLEEP pin. After a

conversion, the SHUTDOWN pin and/or the SLEEP pin of the

ADA4806-1 are pulled low when the ADC input is inactive in

between samples. While in shutdown mode, the ADA4806-1

output impedance is high.

Table 10. System Performance at Selected Input Frequencies for Driving the AD7980 Single-Ended

ADC Driver

Reference Buffer

Results

Input Frequency (kHz)

Supply (V)

Gain

Supply (V)

Gain

SNR (dB)

THD (dBc)

SINAD (dB)

ENOB

1

7.5

1

7.5

1

89.8

103

89.6

14.6

10

7.5

1

7.5

1

89.4

104

89.3

14.5

20

7.5

1

7.5

1

89.9

103

89.7

14.6

50

7.5

1

7.5

1

88.5

99

88.1

14.3

100

7.5

1

7.5

1

86.3

93.7

85.6

13.9

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