CDCE913, CDCEL913

SCAS849F – JUNE 2007 – REVISED APRIL 2015

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6.2 ESD Ratings

VALUE

UNIT

±2000

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101,

±1500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

Device supply voltage

1.7

1.8

1.9

V

2.3

3.6

V

1.7

1.9

Low-level input voltage, LVCMOS

V

High-level input voltage, LVCMOS

V

Input voltage threshold, LVCMOS

V

Input voltage range, S0

0

1.9

V

0

3.6

Input voltage range CLK

0

1.9

V

±12

±10

mA

±8

Output load, LVCMOS

15

pF

Operating free-air temperature

–40

85

°C

Crystal input frequency range (fundamental mode)

8

27

32

MHz

ESR

Effective series resistance

100

Ω

Pulling range (0 V

(2)

±120

±150

ppm

0

V

Pullability ratio

220

On-chip load capacitance at Xin and Xout

0

20

pF

(1)

For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).

(2)

Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120

ppm applies for crystal listed in the application report (SCAA085).

4

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