 2014 Microchip Technology Inc.

DS00001760B-page 31

UPD1002

Note:

Only sourced currents (when the PD port is operating as a provider) can be monitored by IMON. If it is

desired to monitor a sinking current (when the port is operating as a consumer), an external circuit should

be used and the condition indicated to the device via the FAULT_IN_N pin.

3.5

SPI ROM Controller

The device is capable of code execution from an external SPI ROM. On power up, the firmware looks for an external

SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a

valid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in the

external SPI device. If a valid signature is not found, then execution continues from internal ROM. The following sections

describe the interface options to the external SPI ROM.

Note:

Microchip suggests using the SST 25 series serial flash family, such as the SST25VF064C.

3.5.1

OPERATION OF THE HI-SPEED READ SEQUENCE

The SPI controller will automatically handle code reads going out to the SPI ROM Address. When the controller detects

a read, the controller drops the SPI_ROM_CE_N, and puts out a 0x0B, followed by the 24-bit address. The SPI controller

then puts out a DUMMY byte. The next eight clocks clock in the first byte. When the first byte is clocked in a ready signal

is sent back to the processor, and the processor gets one byte.

After the processor gets the first byte, its address will change. If the address is one more than the last address, the SPI

controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI

controller will terminate the transaction by taking SPI_ROM_CE_N high. As long as the addresses are sequential, the

SPI Controller will keep clocking in data.

TABLE 3-7:

IMON OVERCURRENT THRESHOLDS

Negotiated Profile

Current

Overcurrent Threshold (A)

Min.

Typical

Max

1.5 A

-

1.73

1.95

2A

-

2.30

2.60

3A

-

3.45

3.90

5A

-

5.75

6.50

FIGURE 3-2:

SPI ROM HI-SPEED READ OPERATION

SPI

CONTROLLER

SPI

ROM

Serial to

Parllel

CE#

CLK

SI

SO

UPD1002

ADDRESS

CONTROL

CACHE

SPI_ROM_DI