USB3300 datasheet(19/53 Pages) MICROCHIP

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 2014-2015 Microchip Technology Inc.

DS00001783B-page 19

USB3300

6.1.3

ULPI INTERFACE TIMING

The control and data timing relationships are given in Figure 6-3, "ULPI Timing Diagram" and Table 6-2, "ULPI Interface

Timing". The USB300 PHY provides CLKOUT and all timing is relative to the rising clock edge. The timing relationships

detailed below apply to Synchronous Mode only.

6.1.4

ULPI REGISTER ARRAY

The USB3300 PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete

USB3300 ULPI register set is shown in Table 6-3, "ULPI Register Map". All registers are 8 bits. This table also includes

the default states of the register upon POR. The RESET bit in the Function Control Register does not reset the bits of

the ULPI register array. The Link should not read or write to any registers not listed in this table.

FIGURE 6-3:

ULPI TIMING DIAGRAM

TABLE 6-2:

ULPI INTERFACE TIMING

Parameter

Symbol

MIN

MAX

Units

Setup time (control in, 8-bit data in)

TSC,TSD

5.0

Hold time (control in, 8-bit data in)

THC, THD

0ns

Output delay (control out, 8-bit data out)

TDC, TDD

2.0

5.0

Note:

VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40C to 85C; unless otherwise specified.

Clock Out -

CLKOUT

Control In -

STP

Data In -

DATA[7:0]

Control Out -

DIR, NXT

Data Out -

DATA[7:0]

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