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L2G3IS

Digital interfaces

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5

Digital interfaces

The registers embedded inside the L2G3IS may be accessed through the SPI serial

interfaces.

5.1

SPI bus interface

The SPI is a bus slave. The SPI allows to write and read the registers of the device.

The serial interface interacts with the outside world with 3 wires: CS, SCL, SDI/SDO.

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of

the transmission and goes back high at the end. SCL is the serial port clock and it is

controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI/SDO

is the serial port data input and output. This line is driven at the falling edge of SCL and

should be captured at the rising edge of SCL.

Both the read register and write register commands are completed in 16 clock pulses or in

multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling

edges of SCL. The first bit (bit 0) starts at the first falling edge of SCL after the falling edge

of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SCL just before the

rising edge of CS.

5.1.1

SPI write

Figure 6. SPI write protocol

The SPI write command is performed with 16 clock pulses. A multiple byte write command

is performed by adding blocks of 8 clock pulses to the previous one.

bit 0: WRITE bit. The value is 0.

bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in

multiple writes.

bit 2 -7: address AD(5:0). This is the address field of the indexed register.

Table 8. Serial interface pin description

Pin name

Pin description

CS

Chip-select line

SCL

SPI serial port clock

SDI/SDO

SPI serial data input/output

CS

SCL

SDI/SDO

RW

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

AD5 AD4 AD3 AD2 AD1 AD0

MS