M95256-DRMF8TP datasheet(27/41 Pages) STMICROELECTRONICS

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M95256-DRE

Application design recommendations

5.1.3

Power-down

During power-down (continuous decrease in the VCC supply voltage below the minimum

VCC operating voltage defined in Table 12), the device must be:

•

deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC),

•

in Standby power mode (there should not be any internal Write cycle in progress).

5.2

Implementing devices on SPI bus

Figure 16 shows an example of three devices, connected to the SPI bus master. Only one

device is selected at a time, so that only the selected device drives the Serial Data output

(Q) line. All the other devices outputs are then in high impedance.

Figure 16. Bus master and memory devices on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals must be driven high or low as appropriate.

A pull-up resistor connected on each /S input (represented in Figure 16) ensures that each

device is not selected if the bus master leaves the /S line in the high impedance state.

M95256-DRMF8TP Datasheet(PDF) 27 Page - STMicroelectronics