M95040-DRMF4TP datasheet(15/41 Pages) STMICROELECTRONICS

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DocID024225 Rev 6

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M95040-A125 M95040-A145

Instructions

4.1

Write Enable (WREN)

The WREN instruction must be decoded by the device before a write instruction (WRITE,

WRSR, WRID or LID).

As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven low, the

bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D) after what the

Chip Select (S) input is driven high and the WEL bit is set (Status Register bit).

Figure 5. Write Enable (WREN) sequence

4.2

Write Disable (WRDI)

One way of resetting the WEL bit (in the Status Register) is to send a Write Disable

instruction to the device.

As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in (MSB first), on Serial Data Input (D), after

what the Chip Select (S) input is driven high and the WEL bit is reset (Status Register bit).

If a Write cycle is currently in progress, the WRDI instruction is decoded and executed and

the WEL bit is reset to 0 with no effect on the ongoing Write cycle.

In fact, the Write Enable Latch (WEL) bit becomes reset by any of the following events:

•

Power-up

•

WRDI instruction execution

•

WRSR instruction completion

•

WRITE instruction completion

•

Write Protect (W) line being held low.

M95040-DRMF4TP Datasheet(PDF) 15 Page - STMicroelectronics