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C515C Datasheet(PDF) 21 Page - Infineon Technologies AG |
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C515C Datasheet(HTML) 21 Page - Infineon Technologies AG |
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21 / 96 page ![]() C515C Data Sheet 17 2003-02 Control of XRAM/CAN Controller Access The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller. SYSCON Special Function Register (B1H) C515C-8R Reset Value: X010XX01B C515C-8E Reset Value: X010X001B Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. Bit Function XMAP1 XRAM/CAN controller visible access control Control bit for RD/WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0: The signals RD and WR are not activated during accesses to the XRAM/CAN Controller XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally. XMAP0 Global XRAM/CAN controller access enable/disable control XMAP0 = 0: The access to XRAM and CAN controller is enabled. XMAP0 = 1: The access to XRAM and CAN controller is disabled (default after reset). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. 76543210 Bit No. MSB LSB EALE RMAP – B1H SYSCON CSWO XMAP1 –PMOD XMAP0 The function of the shaded bits is not described in this section. |
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